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1 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ? simplified application circuit general description the rt8298 is a synchronous step-down dc/dc converter with an integrated high side internal power mosfet and a gate driver for a low side external power mosfet. it can deliver up to 6a output current from a 4.5v to 24v input supply. the rt8298's current mode architecture allows the transient response to be optimized over a wider input voltage and load range. cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. the rt8298 is synchronizable to an external clock with frequency ranging from 300khz to 1.5mhz. the rt8298 is available in wdfn-14l 4x3 and sop-8 (exposed pad) packages. 6a, 24v, 600khz step-down converter with synchronous gate driver features z z z z z 4.5v to 24v input voltage range z z z z z 6a output current z z z z z 45m internal high side n-mosfet z z z z z current mode control z z z z z 600khz switching frequency z z z z z adjustable output from 0.8v to 15v z z z z z up to 95% efficiency z z z z z internal compensation z z z z z stable with ceramic capacitors z z z z z synchronous external clock : 300khz to 1.5mhz z z z z z cycle-by-cycle current limit z z z z z input under voltage lockout z z z z z output under voltage protection z z z z z power good indicator z z z z z thermal shutdown protection z rohs compliant and halogen free applications z point of load regulator in distributed power system z digital set top boxes z personal digital recorders z broadband communications z flat panel tvs and monitors rt8298 vin c in v in vcc c vcc pgood power good en/sync fb bg sw boot c boot l v out c out r1 r2 chip enable gnd q1
2 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information 04 ym dnn rt8298 zspymdnn rt8298zqw rt8298zsp 04 : product code ymdnn : date code rt8298zsp : product number ymdnn : date code pin configurations (top view) wdfn-14l 4x3 fb pgood vin vin gnd bg vcc sw boot en/sync vin sw nc sw 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 sop-8 (exposed pad) sw boot vcc bg vin en/sync gnd fb gnd 2 3 4 5 6 7 8 9 rt8298 package type qw : wdfn-14l 4x3 (w-type) sp : sop-8 (exposed pad-option 2) lead plating system z : eco (ecological element with halogen free and pb free)
3 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? functional pin description pin no. wdfn-14l 4x3 sop-8 (exposed pad) pin name pin function 1 6 fb feedback input. this pin is connected to the converter output. it is used to set the output of the converter to regulate to the desired value via an external resistive divider. the feedback reference voltage is 0.808v typically. 2 -- pgood power good indicator with open drain. (for rt8298zqw only) a 100k pull-high resistor is needed. the output of this pin is pulled to low when the fb is lower than 0.75v; otherwise it is high impedance. 3 7 en/sync enable or external frequency synchronization input. a logic-high (2v < en < 5.5v) enables the converter; a logic-low forces the ic into shutdown mode reducing the supply current to less than 3 a. for external frequency synchronization operation, the available frequency range is from 300khz to 1.5mhz. 4, 5, 6 8 vin power input. the available input voltage range is from 4.5v to 24v. a 22 f or larger input capacitor is needed to reduce voltage spikes at the input. 7 -- nc no internal connection. 8, 9, 10 1 sw switching node. output of the internal high side mosfet. connect this pin to external low-side n-mosfet, inductor and bootstrap capacitor. 11 2 boot bootstrap for high side gate driver. connect a 1 f ceramic capacitor between the boot pin and sw pin. 12 3 vcc bg driver bias supply. decouple with a 1 f x5r/x7r ceramic capacitor between the vcc pin and gnd. 13 4 bg gate driver output. connect this pin to the gate of the external low-side n-mosfet. 14, 15 (exposed pad) 5, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum thermal dissipation.
4 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? function block diagram operation the rt8298 is a synchronous high voltage buck converter that can support the input voltage range from 4.5v to 24v and the output current can be up to 6a. the rt8298 uses a constant frequency, current mode architecture. in normal operation, the high side n-mosfet is turned on when the switch controller is set by the oscillator (osc) and is turned off when the current comparator resets the switch controller. while the n-mosfet is turned off, the external low side n-mosfet is turned on by bg driver with 5v driving voltage from internal regulator (v cc ) until next cycle begins. high side mosfet peak current is measured by internal r sense . the current signal is where slope compensator works together with sensing voltage of r sense . the error amplifier ea adjusts comp voltage by comparing the feedback signal (v fb ) from the output voltage with the internal 0.808v reference. when the load current increases, it causes a drop in the feedback voltage relative to the reference, the comp voltage then rises to allow higher inductor current to match the load current. uv comparator : if the feedback voltage (v fb ) is lower than threshold voltage 0.4v, the uv comparator's output will go high and the switch controller will turn off the high side mosfet. the output under voltage protection is designed to operate in hiccup mode. oscillator (osc) : the internal oscillator runs at nominal frequency 600khz and can be synchronized by an external clock in the range between 300khz and 1.5mhz from en/ sync pin. pgood comparator : this function is available for rt8298zqw only. when the feedback voltage (v fb ) is higher than threshold voltage 0.75v, the pgood open drain output will be high impedance. enable comparator : internal 5k resistor and zener diode are used to clamp the input signal to 3v. a 1.7v reference voltage is for en logic-high threshold voltage. the en pin can be connected to vin through a 100k resistor for automatic startup. foldback control : when v fb is lower than 0.7v, the oscillation frequency will be proportional to the feedback voltage. soft-start (ss) : an internal current source (6na) charges an internal capacitor (15pf) to build the soft-start ramp voltage (v ss ). the v fb voltage will track the internal ramp voltage during soft-start interval. the typical soft-start time is 2ms. internal regulator + - enable comparator en/sync 1.7v 5k 3v vin osc foldback control + - 1pf 54pf 300k + - ea 0.808v uv comparator + - + - current comparator 0.4v fb boot 45m sw pgood gnd current sense amplifier slope compensator pgood comparator bg driver bg switch controller + - 0.75v vcc r sense v cc + otp comp 6na 15pf v cc v ss v cc current signal
5 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? recommended operating conditions (note 4) z supply input voltage, v in ------------------------------------------------------------------------------------------ 4.5v to 24v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v in ------------------------------------------------------------------------------------------ ? 0.3v to 26v z switching voltage, sw -------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z boot to sw --------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z all other v oltage ---------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdf n-14l 4x3 ------------------------------------------------------------------------------------------------------- 1.667w sop-8 (exposed pad) --------------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) wdfn-14l 4x3, ja ------------------------------------------------------------------------------------------------- 60 c/w wdfn-14l 4x3, jc ------------------------------------------------------------------------------------------------- 7.5 c/w sop-8 (exposed pad), ja ---------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc --------------------------------------------------------------------------------------- 15 c/w z lead temperature (soldering, 10 sec.) ----------------------------------- -------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------ 200v parameter symbol test conditions min typ max unit shutdown supply current v en = 0v -- 1 -- a supply current v en = 3v, v fb = 1v -- 0.9 -- ma feedback reference voltage v ref 4.5v v in 24v 0.796 0.808 0.82 v feedback current i fb v fb = 0.8v -- 10 -- na high-side switch on resistance r ds(on) -- 45 -- m high-side switch current limit boot ? sw = 4.8v -- 10 -- a oscillation frequency f osc1 -- 600 -- khz short circuit oscillation frequency f osc2 v fb = 0v -- 190 -- khz maximum duty cycle d max v fb = 0.6v -- 90 -- % minimum on-time t on v fb = 1v -- 100 -- ns input under voltage lockout threshold v uvlo 4 4.2 4.4 v input under voltage lockout threshold hysteresis v uvlo -- 400 -- mv logic-high v ih 2 -- 5.5 en threshold voltage logic-low v il -- -- 0.4 v (v in = 12v, t a = 25 c, unless otherwise specified) electrical characteristics
6 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? parameter symbol test conditions min typ max unit sync frequency range f sync 0.3 -- 1.5 mhz en turn-off delay t off -- 10 -- s en pull low current v en = 2v -- 1 -- a thermal shutdown t sd -- 150 -- c thermal shutdown hysteresis t sd -- 20 -- c power good threshold rising -- 0.75 -- v power good threshold hysteresis -- 40 -- mv power good pin level pgood sink 10ma -- -- 0.125 v bg driver bias supply voltage v cc 4.5 5 -- v gate driver sink impedance r sink -- 0.9 -- gate driver source impedance r source -- 3.3 -- note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
7 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? typical application circuit for wdfn-14l 4x3 package for sop-8 (exposed pad) package table 1. recommended component selection v out (v) r1 (k ) r2 (k ) l ( h) c out ( f) 1.2 62 127 1.5 22 f x 3 1.8 62 50.5 1.5 22 f x 3 2.5 62 30 2.2 22 f x 3 3.3 62 20 2.2 22 f x 3 5 93 18 2.8 22 f x 3 8 120 13.5 3.6 22 f x 3 rt8298 vin c in 22f v in 4.5v to 24v vcc r3 100k c vcc 1f 4, 5, 6 12 2 pgood power good en/sync 3 1 13 11 fb bg sw boot 8, 9, 10 c boot 1f 2.2h l v out 3.3v c out 22f x 3 62k r1 20k r2 14, 15 (exposed pad) chip enable gnd q1 rt8298 vin c in 22f v in 4.5v to 24v vcc c vcc 1f 8 3 en/sync 7 6 4 2 fb bg sw boot 1 c boot 1f 2.2h l v out 3.3v c out 22f x 3 62k r1 20k r2 5, 9 (exposed pad) chip enable gnd q1
8 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? output voltage vs. temperature 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 12v, v out = 3.3v, i out = 0a output voltage vs. output current 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 output current (a) output voltage (v) v in = 6v v in = 12v v in = 24v v out = 3.3v typical operating characteristics switching frequency vs. input voltage 550 560 570 580 590 600 610 620 630 640 650 4 6 8 1012141618202224 input voltage (v) switching frequency (khz) 1 v out = 3.3v, i out = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0123456 output current (a) efficiency (%) v out = 3.3v v in = 6v v in = 12v v in = 24v output voltage vs. input voltage 3.27 3.28 3.29 3.30 3.31 3.32 3.33 4 6 8 1012141618202224 input voltage (v) output voltage (v) v in = 4.5v to 24v, v out = 3.3v, i out = 0a switching frequency vs. temperature 550 560 570 580 590 600 610 620 630 640 650 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 v in = 12v, v out = 3.3v, i out = 0a
9 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? current limit vs. temperature 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v, v out = 3.3v time (2.5ms/div) power on from vin v in = 12v, v out = 3.3v, i out = 6a v out (2v/div) v in (5v/div) i l (5a/div) time (1 s/div) output ripple voltage v out (10mv/div) v sw (10v/div) i l (5a/div) v in = 12v, v out = 3.3v, i out = 6a time (1 s/div) output ripple voltage v out (10mv/div) v sw (10v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a time (250 s/div) load transient response v out (100mv/div) i out (5a/div) v in = 12v, v out = 3.3v, i out = 0a to 6a time (250 s/div) load transient response v out (100mv/div) i out (5a/div) v in = 12v, v out = 3.3v, i out = 3a to 6a
10 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? time (5ms/div) power off from en v out (2v/div) v en (5v/div) i l (5a/div) v in = 12v, v out = 3.3v, i out = 6a time (500ns/div) external sync v lx (10v/div) clock (5v/div) i l (5a/div) v in = 12v, v out = 3.3v, i out = 6a, clock = 800khz v out (5v/div) time (2.5ms/div) power on from en v out (2v/div) v en (5v/div) i l (5a/div) v in = 12v, v out = 3.3v, i out = 6a time (5ms/div) power off from vin v out (2v/div) v in (5v/div) i l (5a/div) v in = 12v, v out = 3.3v, i out = 6a
11 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? application information output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 1. figure 1. output voltage setting the output voltage is set by an external resistive voltage divider according to the following equation : out ref r1 v = v 1 r2 ?? + ?? ?? where v ref is the feedback reference voltage (0.808v typ.). external bootstrap diode connect a 1 f low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the rt8298. note that the external boot voltage must be lower than 5.5v. figure 2. external bootstrap diode rt8298 gnd fb r1 r2 v out sw boot 5v rt8298 1f chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shutdown the device. during shutdown mode, the rt8298 quiescent current drops to lower than 3 a. driving the en pin high (2v < en < 5.5v) will turn on an external mosfet can be added to implement digital control on the en pin, as shown in figure 4. in this case, a 100k pull-up resistor, r en , is connected between v in pin and the en pin. mosfet q2 will be under logic control to pull down the en pin. figure 3. enable timing control figure 4. digital enable control circuit rt8298 en gnd 100k v in r en q2 en the device again. for external timing control, the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 3). the chip starts to operate when v in rises to 4.2v (uvlo threshold). during the v in rising period, if an 8v output voltage is set, v in is lower than the v out target value and it may cause the chip to shut down. to prevent this situation, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust enable threshold, as shown in figure 5. for example, the setting v out is 8v and v in is from 0v to 12v, when v in is higher than 10v, the chip is triggered to enable the converter. assume r en1 = 50k . then, figure 5. resistor divider for lockout threshold setting rt8298 en gnd v in r en1 r en2 rt8298 en gnd v in r en c en en en1 en_t en2 in_s en_t (r x v ) r = (v v ) ? where v en_t is the enable comparator's logic-high reference threshold voltage (1.7v) and v in_s is the target turn on input voltage (10v in this example). according to the equation, the suggested resistor r en2 is 10.2k .
12 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? figure 6. startup sequence using external sync clock soft-start the rt8298 provides soft-start function. the soft-start function is used to prevent large inrush current while converter is being powered-up. an internal current source (6na) charges an internal capacitor (15pf) to build a soft- start ramp voltage. the v fb voltage will track the internal ramp voltage during soft-start interval. the typical soft- start time is calculated as follows : figure 6 shows the synchronization operation in startup period. when the en/sync is triggered by an external clock, the rt8298 enters soft-start phase and the output voltage starts to rise. when v fb is lower than 0.7v, the oscillation frequency will be proportional to the feedback voltage. with higher v fb , the switching frequency is relatively higher. after startup period about 3.5ms, the ic operates with the same frequency as the external clock. figure 7. hiccup mode under voltage protection ss (0.808v 15pf) t = = 2ms 6na operating frequency and synchronization the internal oscillator runs at 600khz (typ.) when the en/ sync pin is at logic-high level (>2v). if the en pin is pulled to low-level for 10 s above, the ic will shut down. the rt8298 can be synchronized with an external clock ranging from 300khz to 1.5mhz applied to the en/sync pin. the external clock duty cycle must be from 10% to 90%. over temperature protection the rt8298 features an over temperature protection (otp) circuitry to prevent from overheating due to excessive power dissipation. the otp will shut down switching operation when junction temperature exceeds 150 c. once the junction temperature cools down by approximately 20 c, the converter will resume operation. to maintain continuous operation, the maximum junction temperature should be lower than 125 c. under voltage protection for the rt8298, it provides hiccup mode under voltage protection (uvp). when the v fb voltage drops below 0.4v, the uvp function will be triggered to shut down switching operation. if the uv condition remains for a period, the rt8298 will retry every 2ms. when the uv condition is removed, the converter will resume operation. the uvp is disabled during soft-start period. en/sync v fb clk foldback 600khz external clk 3.5ms (start-up period) 10s duty cycle limitation the rt8298 has a maximum duty cycle 90%. the minimum input voltage is determined by the maximum duty cycle and its minimum operating voltage 4.5v. the voltage drops of high side mosfet and low side mosfet also must be considered for the minimum input voltage. the minimum duty cycle can be calculated by the following equation : duty cycle(min) = f sw x t on (min) time (2.5ms/div) hiccup mode v out (1v/div) i l (5a/div) v in = 12v, i out = short
13 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? external n-mosfet selection the rt8298 is designed to operate using an external low side n-mosfet. important parameters for the power mosfets are the breakdown voltage (bv dss ), threshold voltage (v gs_th ), on-resistance (r ds(on) ), total gate charge (qg) and maximum current (i d(max) ). the gate driver voltage is from internal regulator (5v, v cc ). therefore logic level n-mosfet must be used in the rt8298 application. the total gate charge (qg) must be less than 50nc, lower qg characteristics results in lower power losses. drain-source on-resistance (r ds(on) ) should be as small as possible, less than 30m is desirable. lower r ds(on) results in higher efficiency. table 2. external n-mosfet selection part no. manufacture si7114 vishay A04474 alpha & omega fds6670as fairchild irf7821 international rectifier inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can reduce voltage. for the highest efficiency operation, however, it requires a large inductor to achieve this goal. out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? the inductor's current rating (cause a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 3 for the inductor selection reference. table 3. suggested inductors for typical application circuit component supplier series dimensions (mm) 10 x 10 x 4 zenithtek zpw m 6 x 6 x 3 we 74477 10 x 10 x 4 taiyoyuden nr8040 8 x 10 x 4 out in rms out(max) in out v v i = i 1 vv ? c in and c out selection the input capacitance, c in, is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the approximate rms current equation is given : this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. where fsw is the switching frequency, t on (min) is the minimum switch on time (100ns). this equation shows that the minimum duty cycle increases when the switching frequency is increased. therefore, slower switching frequency is necessary to achieve high v in /v out ratio application. for the ripple current selection, the val ue of i l = 0.24(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :
14 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? table 4. suggested capacitors for c in and c out location component supplier part no. capacitance ( f) case size c in mu rata grm31cr61e106k 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yuden tmk316bj106ml 10 1206 c out mu rata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out mu rata grm32er71c226m 22 1210 c out tdk c3225x5r1c22m 22 1210 checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step load change. when a step load occurs, v out immediately shifts by an amount equal to i load x esr also begins to charge or discharge c out generating a feedback error signal for the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the rt8298, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) package, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. the output ripple will be the highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . this ringing can couple to the output and be mistaken. a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for the input capacitor, two 10 f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 4 for more details. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ??
15 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? figure 8. derating curves for rt8298 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 wdfn-14l 4x3 sop-8 (exposed pad) four-layer pcb for wdfn-14l 4x3 package, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-14l 4x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the rt8298 package, the derating curves in figure 8 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout consideration follow the pcb layout guidelines for optimal performance of the rt8298. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep analog components away from the sw node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt8298. ` connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ` an example of pcb layout guide is shown in figure 9 and figure 10 for reference.
16 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? figure 9. pcb layout guide for sop-8 (exposed pad) figure 10. pcb layout guide for wdfn-14l 4x3 v out gnd v out q1 r1 r2 sw boot vcc bg vin en/sync gnd fb gnd 2 3 4 5 6 7 8 9 c in c boot gnd l c out the feedback components must be connected as close to the device as possible. input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the en/sync must be kept away from noise. the trace should be short and shielded with a ground trace. c vcc bg gnd c vcc capacitor must be placed as close to the ic as possible. v in v cc gnd r1 r2 c boot l v out c out v out gnd c in gnd r3 the feedback components must be connected as close to the device as possible. input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the en/sync must be kept away from noise. the trace should be short and shielded with a ground trace. fb pgood vin vin gnd bg vcc sw boot en/sync vin sw nc sw 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 bg c vcc capacitor must be placed as close to the ic as possible. c vcc q1 v in
17 ds8298-01 november 2011 www.richtek.com rt8298 copyright 2011 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.900 4.100 0.154 0.161 d2 3.250 3.350 0.128 0.132 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 14l dfn 4x3 package
18 ds8298-01 november 2011 www.richtek.com rt8298 richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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